As integration density of semiconductor memory devices increases, the separation between adjacent memory cells decreases. Such decrease in separation can cause shorting between adjacent devices.
FIG. 1 illustrates exemplary problems. A semiconductor wafer fragment 10 comprises a bulk substrate 12 having diffusion regions 15 formed therein. Diffusion regions 15 can be part of transistor constructions. Conductive plugs 14 are electrically connected to regions 15 and extend to capacitor constructions 13.
Capacitor constructions 13 comprise a storage node 20, which in the shown example is a hemispherical grain polysilicon (HSG) layer. A dielectric layer 22 is provided over the HSG layer 20 and a conductive layer 24 is formed over dielectric layer 22. Conductive layer 24 defines a capacitor plate for capacitor constructions 13.
Close spacing of adjacent capacitor constructions 13 can inhibit conformal forming of layers 22 and 24, and lead to voids 26 being formed between adjacent capacitor constructions 13. Such voids 26 can undesirably alter dielectric properties at various regions of capacitor constructions 13 relative to other regions of the capacitor constructions 13.
Another problem that can be caused by the close spacing of capacitor constructions 13 is short circuiting between adjacent devices.
Either of the above-discussed problems can detrimentally affect the performance of the memory cells. Accordingly, it is desired to develop new methods of forming conductive devices, and in particular, it is desired to develop new methods of forming capacitor constructions.